Methods and apparatus for an amplifier circuit

ABSTRACT

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may provide a first cross-connect circuit responsive to a first clock signal having a first phase and the third clock signal having a third phase. The amplifier circuit may provide a second cross-connect circuit responsive to a second clock signal having a second phase and a fourth clock signal having a fourth phase. The clock signals have a same frequency with offset phases.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.16/234,729, filed on Dec. 28, 2018, and incorporates the disclosure ofthe application in its entirety by reference.

BACKGROUND OF THE TECHNOLOGY

Many electrical systems utilize an amplifier to amplify low-voltageinput signals. In order to amplify low-voltage input signals, ahigh-gain amplifier is generally required. Amplifiers, however,introduce an offset voltage in the amplifier's output signal, such thatwhen the input signal is amplified, the offset voltage is alsoamplified, which shifts the original operating point of the inputsignal. In general, the higher the gain, the higher the offset (forexample, as illustrated in FIGS. 9-11). In addition, characteristics ofthe output signal, such as the signal-to-noise ratio, dynamic range, andtotal harmonic distortion, deteriorate due to the offset voltage. Inaddition, due to process miniaturization (e.g., 130 nm to 55 nm), thenoise characteristics and the current-voltage characteristics of thetransistors that are used to form the amplifier deteriorate as thetransistors are made smaller and smaller.

SUMMARY OF THE INVENTION

Various embodiments of the present technology may comprise methods andapparatus for an amplifier circuit. Methods and apparatus for anamplifier circuit according to various aspects of the present inventionmay provide a first cross-connect circuit responsive to a first clocksignal having a first phase and the third clock signal having a thirdphase. The amplifier circuit may provide a second cross-connect circuitresponsive to a second clock signal having a second phase and a fourthclock signal having a fourth phase. The clock signals have a samefrequency with offset phases.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

A more complete understanding of the present technology may be derivedby referring to the detailed description when considered in connectionwith the following illustrative figures. In the following figures, likereference numbers refer to similar elements and steps throughout thefigures.

FIG. 1 is a block diagram of a system in accordance with an exemplaryembodiment of the present technology;

FIG. 2 is a clock signal of an analog-to-digital converter and a clocksignal of an amplifier in accordance with an exemplary embodiment of thepresent technology;

FIG. 3 is a circuit diagram of an operational amplifier in accordancewith various embodiments of the present technology;

FIG. 4 is a circuit diagram of a clock generator in accordance with thepresent technology;

FIG. 5 is a circuit diagram of an operational amplifier in accordancewith a first embodiment of the present technology;

FIG. 6 is a timing diagram of an operational amplifier in accordancewith the first embodiment the present technology;

FIG. 7 is a circuit diagram of an operational amplifier in accordancewith a second embodiment the present technology;

FIG. 8 is a timing diagram of an operational amplifier in accordancewith the second embodiment the present technology;

FIG. 9 is a graph illustrating an actual output voltage and a desiredoutput voltage at a first gain;

FIG. 10 is a graph illustrating an actual output voltage and a desiredoutput voltage at a second gain;

FIG. 11 is a graph illustrating an actual output voltage and a desiredoutput voltage at a third gain;

FIG. 12 is a graph illustrating an input signal and a correspondingoutput signal of a conventional amplifier circuit;

FIG. 13 is a graph illustrating an input signal and a correspondingoutput signal in accordance with various embodiments of the presenttechnology;

FIG. 14 is a frequency spectrum of a conventional amplifier circuit;

FIG. 15 is a frequency spectrum of an amplifier circuit in accordancewith various embodiments of the present technology;

FIG. 16 is a graph illustrating an input signal and a correspondingoutput signal of a conventional amplifier circuit; and

FIG. 17 is a graph illustrating an input signal and a correspondingoutput signal according to various embodiments of the presenttechnology.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The present technology may be described in terms of functional blockcomponents and various processing steps. Such functional blocks may berealized by any number of components configured to perform the specifiedfunctions and achieve the various results. For example, the presenttechnology may employ various filters, amplifiers, signal converters,signal processors, and semiconductor devices, such as transistors,capacitors, and the like, which may carry out a variety of functions. Inaddition, the present technology may be practiced in conjunction withany number of electronic systems, such as automotive, aviation, “smartdevices,” portables, and consumer electronics, and the systems describedare merely exemplary applications for the technology. Further, thepresent technology may employ any number of conventional techniques forpulse generation, clock signal generation, voltage regulation, and thelike.

Methods and apparatus for an amplifier circuit according to variousaspects of the present technology may operate in conjunction with anysuitable electronic system, such as an audio system, a microphonesystem, a video telephone, an acoustics system, hearing devices, and thelike.

Referring to FIG. 1, according to various aspects of the presenttechnology, a system 100 may operate in conjunction with or beimplemented in an audio system. According to an exemplary embodiment,the system 100 may comprise an amplifier circuit 105 comprising anoperational amplifier (op-amp) 302 (FIG. 3) connected to variousresistive elements (not shown) and may be configured as a non-invertingamplifier circuit or an inverting amplifier circuit. The system 100 mayfurther comprise a signal processing circuit 110, and ananalog-to-digital converter (ADC) 115. According to various embodiments,the system 100 may receive one or more analog input signals, such asradio signals and/or signal sources from other analog devices, an inputsignal VIN, and generate a corresponding digital output signal.

In general, the system 100 may be described according to variouscharacteristics, such a signal-to-noise ratio (SNR), dynamic range DR,and a total harmonic distortion (THD). The SNR may be described asfollows:

$\begin{matrix}{{{SNR}\mspace{11mu}\lbrack{dB}\rbrack} = {20 \times {{\log\left( \frac{signal}{noise} \right)}.}}} & \left( {{Equation}\mspace{14mu} 1} \right)\end{matrix}$

The dynamic range DR may be described as follows:

DR[dB]=|THD+N|+60   (Equation 2),

where THD+N is the total harmonic distortion with noise at −60 dBFSinput signal. The THD with noise may be described as follows:

$\begin{matrix}{{{{THD} + {N\mspace{11mu}\lbrack{dB}\rbrack}} = {20 \times {\log\left( \frac{\sqrt{{HD}_{2}^{2} + {HD}_{3}^{2} + {HD}_{4}^{2} + \cdots + {HD}_{n}^{2} + {noise}^{2}}}{signal} \right)}}},} & \left( {{Equation}\mspace{14mu} 3} \right)\end{matrix}$

where HD is a harmonic distortion component.

The signal processing circuit 110 may process the one or more inputanalog signals and/or a signal from the amplifier circuit 105. Forexample, the signal processing circuit 110 may comprise a signalselector (not shown) to select one of various analog input signals. Thesignal processing circuit 110 may be configured to perform variousprocessing functions, such as a gain adjustment and/or conversion from asingle-ended signal to a differential signal.

The ADC 115 is configured to convert an analog input signal into adigital signal (i.e., a digital output). According to an exemplaryembodiment, the ADC 115 is configured as an over-sampling type, discretetime ADC. For example, the ADC 115 may comprise an input analog circuitcomponent, such as a delta sigma modulator (not shown), connected tooutput digital circuit component, such as a decimation filter (notshown) and high pass filter (not shown). The ADC 115 may operateaccording to an ADC clock signal ADC_CLK.

The decimation filter and the high pass filter may operate together toperform noise shaping and sampling functions. In addition, thedecimation filter may be configured to remove a clock signal component,such as the clock signals CLK1:CLK4, from the analog input signal.

According to an exemplary embodiment, and referring to FIGS. 1 and 2,the system 100 may further comprise a clock divider 120 configured togenerate an amplifier clock signal AMP_CLK. For example, the clockdivider 120 may divide the ADC clock signal ADC_CLK by a value N, whereN is a natural number and is selected according to desired operatingconditions and/or a sampling frequency f_(s) of the system 100. In otherwords, the amplifier clock signal AMP_CLK is proportional to the ADCclock signal ADC_CLK by a factor of 1/N. According to an exemplaryembodiment, the amplifier clock signal AMP_CLK has a frequency that ishigher than the sampling frequency f_(s) of the system 100 and lowerthan an operating frequency of the ADC 115. Therefore, the value N maybe selected to achieve these conditions. For example, if the samplingfrequency f_(s) is 48 kHz, then the ADC operating frequency may be 6.144MHz (which is 128 times the sampling frequency f_(s)), and the amplifierclock signal AMP_CLK may be 192 kHz (which is 4 times the samplingfrequency). Furthermore, the frequency of the amplifier clock signalAMP_CLK is set to a notch frequency of the decimation filter. Also, thedecimation filter is able to efficiently remove the amplifier clockcomponent (AMP_CLK) from an output signal VOUT of the amplifier circuit105.

According to an exemplary embodiment, a rising edge of the amplifierclock signal AMP_CLK is not aligned with a rising edge or a falling edgeof the ADC clock signal ADC_CLK. The clock divider 120 may then transmitthe amplifier clock signal AMP_CLK to a clock generator 325 and/or theamplifier circuit 105.

According to an exemplary embodiment, and referring to FIGS. 3, 4 and 6,the op-amp 302 may be configured to operate according to a plurality ofclock signals. For example, the system 100 may comprise the clockgenerator 325 configured to generate a first clock signal CLK1, a secondclock signal CLK2, a third clock signal CLK3, and a fourth clock signalCLK4. According to an exemplary embodiment, each clock signal isassociated with a corresponding phase, wherein each phase is offset fromthe other phases, and all the clock signals CLK1:CLK4 have the samefrequency. In other words, a rising edge for each clock signal occur atdifferent times. For example, the first clock signal CLK1 may have afirst phase ϕ1, the second clock signal CLK2 may have a second phase ϕ2,the third clock signal CLK3 may have third phase ϕ3, and the fourthclock signal CLK4 may have a fourth phase ϕ4.

The clock generator 325 may comprise any circuit and/or system suitablefor generating a plurality of clock signals, each with a differentphase, according to a reference clock signal, such as the amplifierclock signal AMP_CLK. For example, the clock generator 325 may comprisea plurality of inverters IV0:IV12 and a first NOR gate NOR1 and a secondNOR gate NOR2 arranged as illustrated in FIG. 4.

According to various embodiments, and referring to FIGS. 3, 5, and 7,the op-amp 302 receives the input voltage V_(IN) and amplifies the inputvoltage V_(IN) to generate the output signal V_(OUT) (i.e., an outputvoltage). The op-amp 302 may comprise an inverting terminal (not shown)and a non-inverting terminal (not shown) to receive a first input signalV_(IN_P) (i.e., a first voltage) and a second input signal V_(IN_N)(i.e., a second voltage), and an output terminal to transmit the outputsignal V_(OUT) to the signal processing circuit 110. The op-amp 302 maybe formed as an integrated circuit and configured as a single-endedop-amp.

The op-amp 302 may comprise various circuits that operate together toremove or reduce an offset voltage of the output signal V_(OUT) andremove or reduce noise in the output signal V_(OUT). The op-amp 302 maycomprise circuitry configured to modulate and demodulate the inputsignals. For example, the op-amp 302 may comprise a first cross-connectcircuit 310, a second cross-connect circuit 320, and a voltageadjustment circuit 315. According to an exemplary embodiment, the op-amp302 may be further configured to perform multiple gain stages. Forexample, the op-amp 302 may comprise an input stage circuit 300 toperform a first gain stage and an output stage circuit 305 to perform asecond gain stage.

The first cross-connect circuit 310 is configured to modulate the firstand second input signals VIN_N, V_(IN_P) by selectively transmitting thefirst and second input signals V_(IN_N), V_(IN_P) to the input stagecircuit 300. In addition, the first cross-connect circuit 310 is locatedin a position that best minimizes a voltage difference of the inputsignals V_(IN_N), V_(IN_P). This configuration doesn't form a DC currentpath, therefore, a current of the input stage circuit 300 is stable. Forexample, the first cross-connect circuit 310 may comprise a plurality ofswitches, such as a first switch SW1, a second switch SW2, a thirdswitch SW3, and a fourth switch SW4. The first and second switches SW1,SW2 may be directly connected to the second input signal V_(IN_P) andthe third and fourth switches SW3, SW4 may be directly connected to thefirst input signal V_(IN_N). Each switch SW1:SW4 may be implemented as atransistor. For example, and referring to FIG. 7, each switch SW1:SW4may be implemented as an n-channel transistor (NMOS) when second andthird transistors M2, M3 comprise p-channel transistors (PMOS).Referring to FIG. 5, each switch SW1:SW4 may be implemented as ap-channel transistor when the second and third transistors M2, M3comprises n-channel transistors.

The first and third switches SW1, SW3 may be connected in series witheach other, and the second and fourth switches SW2, SW4 may be connectedin series with each other. Each series-connected circuit may beconnected in parallel with each other. Each switch SW1:SW4 may be incommunication with the clock generator 325 and configured to operateaccording to a particular clock signal. According to an exemplaryembodiment, the first and fourth switches SW1, SW4 may receive andrespond to the first clock signal CLK1 and operate according to thefirst phase ϕ1, and the second and third switches SW2, SW3 may receiveand respond to the third clock signal CLK3 and operate according to thethird phase ϕ3.

The input stage circuit 300 is configured to perform a first gain stageand apply a first gain to the first and second input signals V_(IN_N),V_(IN_P). For example, the input stage circuit 300 may comprise aplurality of transistors, such as a first transistor M1, a secondtransistor M2, a third transistor M3, a fourth transistor M4, and afifth transistor M5. The first transistor M1 may be configured toprovide a current. For example, the first transistor M1 may receive afirst bias voltage V_(BIAS1) at a gate terminal and a reference voltage,such as a supply voltage V_(DD) or a ground GND, at a source/drainterminal.

The second and third transistors M2, M3 may be connected to the firsttransistor M1 and configured to form a differential pair. The fourthtransistor M4 may be connected to the second transistor M2 at a firstnode N1 and the fifth transistor M5 may be connected to the thirdtransistor M3 at a second node N2. The fourth and fifth transistors M4,M5 may be connected to each other via gate terminals of each. The fourthand fifth transistors M4, M5 may also receive a second bias voltageV_(BIAS2) at the respective gate terminals.

The input stage circuit 300 may be connected to the first cross-connectcircuit 310 and receive the first and second input signals V_(IN_N),V_(IN_P) according to the first cross-connect circuit 310. For example,the second transistor M2 may be connected to a third node N3 locatedbetween the first and third switches SW1, SW3 via a gate terminal of thesecond transistor M2. The third transistor M3 may be connected to afourth node N4 located between the second and fourth switches SW2, SW4via a gate terminal of the third transistor M3.

The second cross-connect circuit 320 is configured to selectivelytransmit signals from the input stage circuit 300 to the output stagecircuit 305. In addition, the second cross-connect circuit 320 islocated in a position that best minimizes a voltage difference of thefirst and second nodes N1, N2. This configuration doesn't form a DCcurrent path, therefore, a current of the input stage circuit 300 andthe output stage circuit 305 is stable. For example, the secondcross-connect circuit 320 may comprise a plurality of switches, such asa fifth switch SW5, a sixth switch SW6, a seventh switch SW7, and eighthswitch SW8. The fifth and sixth and second switches SW5, SW6 may beconnected to the first node N1 and the seventh and eight switches SW7,SW8 may be connected to the second node N2. Each switch SW5:SW8 may beimplemented as a transistor. For example, and referring to FIG. 7, eachswitch SW5:SW8 may be implemented as an n-channel transistor (NMOS) whensecond and third transistors M2, M3 comprise p-channel transistors(PMOS). Referring to FIG. 5, each switch SW5:SW8 may be implemented as ap-channel transistor when the second and third transistors M2, M3comprises n-channel transistors.

In addition, the fifth and seventh switches SW5, SW7 may be connected inseries with each other at a fifth node N5, and the sixth and eighthswitches SW6, SW8 may be connected in series with each other at a sixthnode N6. Each series-connected circuit may be connected in parallel witheach other. Each switch SW5:SW8 may be in communication with the clockgenerator 325 and configured to operate according to a particular clocksignal. According to an exemplary embodiment, the fifth and eightswitches SW5, SW8 may receive and respond to the second clock signalCLK2 and operate according to the second phase ϕ2, and the sixth andseventh switches SW6, SW7 may receive and respond to the fourth clocksignal CLK4 and operate according to the fourth phase ϕ4.

The voltage adjustment circuit 315 may be configured to regulate and/oradjust a voltage of the input stage circuit 300. For example, thevoltage adjustment circuit 315 may ensure that a drain voltage level forthe fourth and fifth transistors M4, M5 are equal. Furthermore, thevoltage adjustment circuit 315 may not comprise any switching devices,which provides a stable current to the input stage circuit 300.

According to an exemplary embodiment, the voltage adjustment circuit 315may comprise a plurality of transistors, such as a sixth transistor M6,a seventh transistor M7, and an eighth transistor M8. The sixthtransistor M6 may be configured to provide a current. For example, thesixth transistor M6 may receive a third bias voltage V_(BIAS3) at a gateterminal and be connected to the first transistor M1 at a source/drainterminal. In addition, the sixth transistor M6 may be directly connectedto the first transistor M1 and therefore, the voltage adjustment circuit315 shares a current source (e.g., the first transistor M1) with theinput stage circuit 300. According to an exemplary embodiment, thefirst, second, and third bias voltages V_(BIAS1), V_(BIAS2), V_(BIAS3)are all different voltage values.

The seventh and eighth transistors M7, M8 may be connected to asource/drain terminal of the sixth transistor M6 via source/drainterminals of the seventh and eighth transistors M7, M8. A gate terminalof the seventh transistor M7 may be connected to the second node N2 anda gate terminal of the eighth transistor M8 may be connected to thefirst node N1.

The output stage circuit 305 is configured to perform a second gainstage and apply a second gain to the first and second input signalV_(IN_N), V_(IN_P) and generate the output signal V_(OUT). For example,the output stage circuit 305 may comprise a plurality of transistors,such as a ninth transistor M9, a tenth transistor M10, an eleventhtransistor M11, a twelfth transistor M12. The output stage circuit 305may further comprise resistive elements, such a resistors RZ1 and RZ2and capacitive elements, such as capacitors CC1 and CC2.

The output stage circuit 305 may receive signals from the secondcross-connect circuit 320. For example, the output stage circuit 305 maybe connected the fifth node N5 (located between the fifth and seventhswitches SW5, SW7) and the sixth node N6 (located between the sixth andeighth switches SW6, SW8) of the second cross-connect circuit 320.

In operation, and according to various embodiments, the op-amp 302 mayexhibit an output signal V_(OUT) with little to no offset and low noisecharacteristics. For example, and referring to FIG. 17, given aparticular input signal, the output signal is an amplified version ofthe input signal and does not exhibit an offset. In contrast, andreferring to FIG. 16, given a particular input signal, a conventionalop-amp will generate an amplified output with an offset.

Referring to FIG. 13, and according to the present technology, given aparticular input signal, the output signal of the op-amp 302 is notaffected by flicker and thermal noise. In contrast, and referring toFIG. 12, given a particular input signal, the output signal of aconventional op-amp exhibits an offset when flicker and thermal noiseare present. Referring to FIG. 15, and according to the presenttechnology, the low noise and low offset characteristics may also beobserved in a frequency spectrum plot. In contrast, and referring toFIG. 14, noise and offset may be observed in a frequency spectrum plotof a conventional op-amp.

According to an exemplary operation, and referring to FIGS. 7 and 8, thefirst cross-connect circuit 310 receives the first and second inputsignals V_(IN_N), V_(IN_P). The first, fourth, fifth, and eighthswitches SW1, SW4, SW5, SW8 are closed, while the second, third, sixthand seventh switches SW2, SW3, SW6, SW7 are open. After some period oftime, the first and fourth switches SW1, SW4 open. The fifth and eighthswitches SW5, SW8 are also closed during a period of time commensuratewith that of the first and fourth switches SW1, SW4 but open at sometime after the first and fourth switches SW1, SW4 open. After the fifthand eighth switches SW5, SW8 open, the sixth and seventh switches SW6,SW7 close. After the sixth and seven switches SW6, SW7 close, the secondand third switches SW2, SW3 close. During operation, a period of timeexists where all switches SW1:SW 8 are open (shown in shaded region).

According to an alternative embodiment, and referring to FIGS. 5 and 6,the first cross-connect circuit 310 receives the first and second inputsignals V_(IN_N), V_(IN_P). The first, fourth, fifth, and eighthswitches SW1, SW4, SW5, SW8 are open, while the second, third, sixth andseventh switches SW2, SW3, SW6, SW7 are closed. After some period oftime, the first and fourth switches SW1, SW4 close. The fifth and eighthswitches SW5, SW8 are also open during a period of time commensuratewith that of the first and fourth switches SW1, SW4 but close at sometime after the first and fourth switches SW1, SW4 close. After the fifthand eighth switches SW5, SW8 close, the sixth and seventh switches SW6,SW7 open. After the sixth and seven switches SW6, SW7 open, the secondand third switches SW2, SW3 open. During operation, a period of timeexists where all switches SW1:SW8 are open (shown in shaded region).

In the foregoing description, the technology has been described withreference to specific exemplary embodiments. The particularimplementations shown and described are illustrative of the technologyand its best mode and are not intended to otherwise limit the scope ofthe present technology in any way. Indeed, for the sake of brevity,conventional manufacturing, connection, preparation, and otherfunctional aspects of the method and system may not be described indetail. Furthermore, the connecting lines shown in the various figuresare intended to represent exemplary functional relationships and/orsteps between the various elements. Many alternative or additionalfunctional relationships or physical connections may be present in apractical system.

The technology has been described with reference to specific exemplaryembodiments. Various modifications and changes, however, may be madewithout departing from the scope of the present technology. Thedescription and figures are to be regarded in an illustrative manner,rather than a restrictive one and all such modifications are intended tobe included within the scope of the present technology. Accordingly, thescope of the technology should be determined by the generic embodimentsdescribed and their legal equivalents rather than by merely the specificexamples described above. For example, the steps recited in any methodor process embodiment may be executed in any order, unless otherwiseexpressly specified, and are not limited to the explicit order presentedin the specific examples. Additionally, the components and/or elementsrecited in any apparatus embodiment may be assembled or otherwiseoperationally configured in a variety of permutations to producesubstantially the same result as the present technology and areaccordingly not limited to the specific configuration recited in thespecific examples.

Benefits, other advantages and solutions to problems have been describedabove with regard to particular embodiments. Any benefit, advantage,solution to problems or any element that may cause any particularbenefit, advantage or solution to occur or to become more pronounced,however, is not to be construed as a critical, required or essentialfeature or component.

The terms “comprises”, “comprising”, or any variation thereof, areintended to reference a non-exclusive inclusion, such that a process,method, article, composition or apparatus that comprises a list ofelements does not include only those elements recited, but may alsoinclude other elements not expressly listed or inherent to such process,method, article, composition or apparatus. Other combinations and/ormodifications of the above-described structures, arrangements,applications, proportions, elements, materials or components used in thepractice of the present technology, in addition to those notspecifically recited, may be varied or otherwise particularly adapted tospecific environments, manufacturing specifications, design parametersor other operating requirements without departing from the generalprinciples of the same.

The present technology has been described above with reference to ane6xemplary embodiment. However, changes and modifications may be made tothe exemplary embodiment without departing from the scope of the presenttechnology. These and other changes or modifications are intended to beincluded within the scope of the present technology, as expressed in thefollowing claims.

1. An amplifier, comprising: a first cross-connect circuit responsive toa first clock signal having a first phase and a third clock signalhaving a third phase and configured to receive a first input signal anda second input signal; a second cross-connect circuit responsive to asecond clock signal having a second phase and a fourth clock signalhaving a fourth phase; an input stage circuit connected between thefirst cross-connect circuit and the second cross-connect circuit; and anoutput stage circuit connected to an output terminal of the secondcross-connect circuit and configured generate an output voltage;wherein: at a first time, the first and second clock signals have afirst signal level; at a second time, the first, second, third, andfourth signals have a second signal level; and at a third time, thethird and fourth clock signals have the first signal level and the firstand second clock signals have the second signal level.
 2. The amplifieraccording to claim 1, wherein: each of the first, second, third, andfourth phases are offset from each other; and the first, second, third,and fourth clock signals have a same frequency.
 3. The amplifieraccording to claim 1, wherein the first cross-connect circuit comprises:a first switch responsive to the first clock signal; a second switch inparallel with the first switch and responsive to the third clock signal;a third switch in series with the first switch and responsive to thethird clock signal; and a fourth switch in series with the second switchand responsive to the first clock signal.
 4. The amplifier according toclaim 3, wherein: the first cross-connect circuit comprises a third nodelocated between the first and third switches and a fourth node locatedbetween the second and fourth switches; and the input stage circuitcomprises a differential transistor pair comprising a first transistorand a second transistor, wherein the first transistor is connected tothe third node and the second transistor is connected to the fourthnode.
 5. The amplifier according to claim 1, where the secondcross-connect circuit comprises: a fifth switch responsive to the secondclock signal; a sixth switch in parallel with the fifth switch andresponsive to the fourth clock signal; a seventh switch in series withthe fifth switch and responsive to the fourth clock signal; and aneighth switch in series with the sixth switch and responsive to thesecond clock signal.
 6. The amplifier according to claim 1, wherein theinput stage circuit is responsive to a first bias voltage and a secondbias voltage.
 7. The amplifier according to claim 6, wherein theamplifier further comprises a voltage adjustment circuit connected tothe input stage circuit and responsive to a third bias voltage.
 8. Amethod for operating a system having an amplifier with a first circuit,a second circuit, and a third circuit, comprising: generating: a firstclock signal having a first phase; a second clock signal having a secondphase; a third clock signal having a third phase; and a fourth clocksignal having a fourth phase; wherein: at a first time, the first andsecond clock signals have a first signal level; at a second time, thefirst, second, third, and fourth signals have a second signal level; andat a third time, the third and fourth clock signals have the firstsignal level and the first and second clock signals have the secondsignal level; operating the first circuit according to the first clocksignal and the third clock signal; and operating the second circuitaccording to the second clock signal and the fourth clock signal.
 9. Themethod according to claim 8, wherein the first, second, third, andfourth clock signals are generated based on a first reference clocksignal.
 10. The method according to claim 9, further comprisingoperating the third circuit according to a second reference clocksignal.
 11. The method according to claim 10, wherein the firstreference clock signal is proportional to the second reference clocksignal by a factor of 1/N, where N is a natural number.
 12. The methodaccording to claim 8, wherein: each of the first, second, third, andfourth phases are offset from each other; and the first, second, third,and fourth clock signals have a same frequency.
 13. The method accordingto claim 8, further comprising operating the amplifier according to afirst bias voltage, a second bias voltage, and a third bias voltage. 14.A system, comprising: a clock generator configured to generate: a firstclock signal having a first phase; a second clock signal having a secondphase; a third clock signal having a third phase; and a fourth clocksignal having a fourth phase; wherein: at a first time, the first andsecond clock signals have a first signal level; at a second time, thefirst, second, third, and fourth signals have a second signal level; andat a third time, the third and fourth clock signals have the firstsignal level and the first and second clock signals have the secondsignal level; an amplifier configured to generate an output signal inresponse to the first, second, third, and fourth clock signals; and ananalog-to-digital converter (ADC) connected to the amplifier configuredto convert the output voltage to a digital signal.
 15. The systemaccording to claim 14, wherein the clock generator generates the first,second, third, and fourth clock signals based on a reference clocksignal.
 16. The system according to claim 15, wherein: the ADC isresponsive to an ADC clock; and the reference clock signal isproportional to the ADC clock by a factor of 1/N, where N is a naturalnumber.
 17. The system according to claim 14, wherein: each of thefirst, second, third, and fourth phases are offset from each other; andthe first, second, third, and fourth clock signals have a samefrequency.
 18. The system according to claim 14, wherein the amplifiercomprises: a first cross-connect circuit comprising: a first switchresponsive to the first clock signal; a second switch in parallel withthe first switch and responsive to the third clock signal; a thirdswitch in series with the first switch and responsive to the third clocksignal; and a fourth switch in series with the second switch andresponsive to the first clock signal; and a second cross-connect circuitcomprises: a fifth switch responsive to the second clock signal; a sixthswitch in parallel with the fifth switch and responsive to the fourthclock signal; a seventh switch in series with the fifth switch andresponsive to the fourth clock signal; and an eighth switch in serieswith the sixth switch and responsive to the second clock signal.
 19. Thesystem according to claim 18, wherein the amplifier further comprises:an input stage circuit connected to the first cross-connect circuit andresponsive to a first bias voltage and a second bias voltage; and anoutput stage circuit connected to an output terminal of the secondcross-connect circuit and configured to generate the output voltage. 20.The system according to claim 19, wherein the amplifier furthercomprises a voltage adjustment circuit connected to the input statecircuit and responsive to a third bias voltage.